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Espressif Systems /ESP32-S3 /I2S0 /INT_ENA

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Interpret as INT_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_DONE_INT_ENA)RX_DONE_INT_ENA 0 (TX_DONE_INT_ENA)TX_DONE_INT_ENA 0 (RX_HUNG_INT_ENA)RX_HUNG_INT_ENA 0 (TX_HUNG_INT_ENA)TX_HUNG_INT_ENA

Description

I2S interrupt enable register.

Fields

RX_DONE_INT_ENA

The interrupt enable bit for the i2s_rx_done_int interrupt
TX_DONE_INT_ENA

The interrupt enable bit for the i2s_tx_done_int interrupt
RX_HUNG_INT_ENA

The interrupt enable bit for the i2s_rx_hung_int interrupt
TX_HUNG_INT_ENA

The interrupt enable bit for the i2s_tx_hung_int interrupt

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data